The present invention relates generally to the structure of a full fill factor image array and its method of manufacture, and more particularly to the structure of a full fill factor image array that reduces lateral leakage current and its method of manufacture.
A conventional image array is typically formed of a plurality of photosensitive elements or pixels arranged in rows and columns. A conventional photosensitive element is shown in FIG. 1. Each photosensitive element (10) comprises photosensitive island (12) of amorphous silicon (a-Si) over a bottom contact pad (14) over a substrate (11). A transparent upper conductive layer (16) of indium tin oxide (ITO) resides over the assembly. A passivation layer (18) is disposed under the ITO (16) except where the ITO is in electrical contact with the upper surface of the of the photosensor island (12). The photosensitive element further includes a N+ doped region (22) and a P+ doped region (24). A conventional passivation layer (18) comprises an oxyinitride layer (26) and a polyamide layer (28).
In contrast to the conventional image arrays in which each pixel is defined by a stand alone PIN photosensitive element, the full fill factor image array improves the pixel fill factor by using continuous layers of amorphous silicon (a-Si) and P+ doped a-Si. The pixels in a high fill factor array are defined only by a mushroom shaped collection electrode.
A conventional full fill factor image array is shown in FIG. 2. The full fill factor image array (40) includes a plurality of source-drain metal contacts (44) on a substrate (42). For ease of description, other elements that may be formed on the substrate, such as gate lines, data lines, and thin film transistors (TFTs) are not shown. The source-drain metal contacts (44) are formed of an electrically conductive material such as a molybdenum and chromium alloy. They typically comprise one or more layers of metal. The source-drain metal contacts (44) are electrically connected to the switching and processing circuits (not shown).
To increase the area of carrier collection, a patterned mushroom-shaped collection electrode (46) is provided over the source-drain metal (44). Disposed on top of the mushroom shaped collection electrode is an N+ doped a-Si layer (48).
In contrast to a conventional image array using stand alone PIN photosensitive elements, the full fill factor image array uses a continuous intrinsic amorphous silicon (i a-Si) layer (50) and a continuous P+ doped a-Si layer (52). An upper electrode (54) of ITO resides on top of the P+ doped a-Si layer.
A conventional passivation layer comprises an oxynitride layer (56) deposited to thickness of about 1 micron by plasma enhanced chemical vapor deposition (PECVD). The passivation layer serves as the insulation between the source-drain metal (44) and photosensor (46, 48, and 50)
Like conventional photosensitive elements, the sensor structure of conventional full fill factor image arrays suffers from intrinsic leakage. Intrinsic leakage (58), represented in FIG. 2, arises due to material defects rather than the structure of the photosensitive element. The intrinsic leakage current of a 60xc3x9760 xcexcm2 stand alone PIN sensor, for example, is about 2 femto amp (fA). In addition to intrinsic leakage, however, the conventional full fill factor image array structure suffers lateral leakage between pixels. This lateral leakage current causes image blurring effects and severely reduces the imager performance. The lateral leakage current for a 60xc3x9760 xcexcm2 full fill factor array may be as high as 0.3 pico-amps (pA) at 5 V.
The bulk conductivity of high quality intrinsic a-Si is less than 10xe2x88x9211 (xcexa9xc2x7cm)xe2x88x921 which is about 2xc3x971014 xcexa9 between a 60xc3x9760 xcexcm2 pixel and its neighbor. Therefore, the intrinsic bulk conductivity of a-Si cannot be responsible for the high lateral leakage current. The most likely conducting mechanism for this lateral leakage current is conduction through the accumulated charge in the a-Si and oxynitride interface. Both the trapped positive ion in the oxynitride and the interface states in the a-Si/oxynitride interface can cause electron accumulation in the a-Si/oxynitride interface, creating a conducting channel between pixels.
One solution is to replace the passivation layer with another dielectric material such as silicon oxide or silicon nitride. Deposition rates for silicon oxide or silicon nitride, however, are usually much lower than for oxynitride. Therefore, deposition of a silicon nitride or silicon oxide passivation layer of about 1 micron would be impractical. In addition, other problems such as stress build-up may degrade the sensor structure.
In light of the foregoing, there is a need for a method and structure to reduce the lateral leakage current in full fill factor sensor arrays.
Accordingly, the present invention is directed to a high fill factor image array including a plurality of source-drain metal contacts disposed in an image array pattern, a dual dielectric passivation layer that suppresses lateral leakage current comprising a first passivation layer and a second passivation layer deposited over the first passivation layer, wherein the thickness of the second passivation layer is less than the thickness of the first passivation layer, a continuous layer of a-Si, a plurality of a patterned collection electrodes disposed on top of the source-drain metal contacts, a first doped silicon layer disposed over the collection electrodes a continuous second doped silicon layer, and an upper electrode.
In another aspect, the invention is directed to a method for making a high fill factor image array including the steps of providing a plurality of source-drain metal contacts, depositing a first passivation layer, depositing a second passivation layer that suppresses lateral leakage current, opening a plurality of via holes through the first and second passivation layers, depositing a layer of conductive material, depositing a first doped a-Si layer, patterning to form the collection electrodes, depositing a continuous layer of i a-Si, depositing a continuous second layer of doped a-Si, depositing and patterning an upper conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description serve to explain the principles of the invention.